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Published May 7, 2018 | Version v1

Development of a Level-1 Track and Vertex Finder for the Phase II CMS experiment upgrade

Authors/Creators

  • 1. Bristol U
  • 1. Bristol U
  • 2. Rutherford

Description

The High Luminosity (HL-LHC) upgrade to the Large Hadron Collider will operate at an increased instantaneous luminosity, up to seven times the design value, in order to collect an integrated luminosity of $3,000$\,fb$^{-1}$ in the decade following 2025. Proton bunches at the HL-LHC will cross every $25$\,ns, producing an average of 140-200 pile-up proton-proton collisions per crossing. A new tracking detector is under development for use by the CMS experiment at the HL-LHC. A crucial requirement of this upgrade is to provide the ability to reconstruct charged particle tracks with transverse momentum above $2$--$3$\,GeV within $4\,\upmu$s to be used in the Level-1 (L1) trigger decision. This thesis presents one of the main proposals for the final L1 Track Finding system, which exploits a fully time-multiplexed architecture based on high-speed FPGA electronics. The developed track finding algorithm makes use of the Hough Transform technique to identify track candidates, followed by a track fitting stage. Several options for the track fitting task have been explored. One of the most promising has been identified in the so-called Seed Filter plus Linear Regression fitter. The chosen track finding algorithm is able to reconstruct efficiently tracks from charged particles with a processing latency well below the assigned budget. A hardware demonstrator has been built using existing CMS data processing boards, known as MP7, and has proved the feasibility to perform track finding at the HL-LHC within the assigned latency with good reconstruction efficiency. The thesis explores also a possible use of the L1 tracks to identify primary vertices at the L1 Trigger stage. Several clustering algorithms have been studied. The Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm has been found as the most promising option for a final application, showing good performance and being feasible for an FPGA implementation.

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CERN-THESIS-2018-045.pdf

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Additional details

Identifiers

CDS
2317060
CDS Report Number
CERN-THESIS-2018-045
CDS Report Number
CMS-TS-2018-013

CERN

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